Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter

In conventional memory-based multiplication design, the multiplier is replaced by a read only memory (ROM). Since the memory size increases exponentially with the input length, in this paper, a modified hardwareefficient approach for memoryless-based multiplication is proposed. The very large scale integration (VLSI) measure indicates that the proposed approach involves less hardware complexity compared with the existing one. Then the proposed approach is applied in the finite impulse response (FIR) filter. It is observed that the proposed memorylessbased multiplication can be decomposed into a number of small units. Thus, we present the design optimization of onedimensional (1-D) and two-dimensional (2-D) fully systolic arrays for area-delay-efficient implementation of finite impulse response (FIR) filter, using the proposed memoryless-based multiplier. For efficient realization of FIR filters of different orders, the systolic designs are synthesized by Synopsys Design Compiler along with the FIR filter using the existing lookup table (LUT)-based multiplier. The key measure metric, namely the area-delay product is estimated for different filter orders. Analysis of the result obtained indicates that the proposed 2-D structure involves significantly less area-time complexity when compared to the FIR filter using the existing LUT-based multiplier. Besides, the 2-D systolic array is found to offer a fixed duration of cycle period for each processing element (PE), and therefore suits well for filter implementation with large filter order.